On the previous entry of this series we went through the VHDL source file and simulation of a Timer component.
In this entry, we will instantiate several Timer components to create a timer bank (or block of timers).
The code is attached below:
The load_sel signal is an address bus that selects which timer to initialize. The data used to initialize the selected timer is present at the data_in bus. When the load signal is asserted, the timer addressed by the value present on load_sel is initialized with the data on data_in.
Each timer can be enabled or disabled independently by its corresponding bit in the en vector. Any timer that reaches the timing end (value = zero), asserts its corresponding bit on the done_vec output vector. A disabled timer does not output done.
The architecture has two major blocks. The demux process delivers the load signal to the timer addressed by load_sel.
The timers themselves are instantiated on the GEN_TIMER generate loop.
On the first entry of this series, the parameter DATA_W of the timer component was passed as a generic. In this article of the series we present an alternative way of parameterizing designs, namely, to use a package file. The package file for this design is shown below:
As we see, the implementation consists of 16 timers of 32 bits each. Notice the usage of ceil and log2 functions to calculate the width of the addressing vector automatically from the timers’ quantity.
The design was going to be implemented in a Cyclone IV EP4CE10E22. This device has 10,200 Logic Elements (LEs). The minimum expected quantity of LE was 16 x 32, or approx. 512 LE. However, after synthesis, it was apparent that the generated combinatorial logic was dominant over the sequential one, and the final size of the block was more than 700 LEs, which represents around 7% of the total LEs of the device.
We didn’t want to occupy so much space of the device with the timers block. In the next entry of this series, we will explain how we avoided taking so many LEs from the device for this block.
See you next time!
The source files for this design are available here.