VHDL arbiter (III)

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This is the third part of a series of articles on VHDL arbiters.

On the first part, we commented what a VHDL arbiter is.

On the second part, we saw the VHDL code for a fixed priority VHDL arbiter.

When I talked about what a VHDL arbiter is, I gave the example of the single car we have at home, and how I have to decide who gets to use the car on next Friday evening. In a typical situation, if both children ask for the car, the first thing they will account for is, who got the car the last time.

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Internet of Things (IoT) – Overview whitepaper

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Understanding the Issues and Challenges of a More Connected World

by Karen Rose
Senior Director, Strategy & Analysis

Reproduced from the Internet Society

Promising to transform the ways we live, work, and play, the Internet of Things (IoT) offers impressive benefits but presents significant challenges.

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VHDL Arbiter – part II

In the previous installment, we defined what a HW arbiter is. Let’s see a simple implementation of a VHDL arbiter.

The arbiter has three inputs and three outputs.

The logic is very simple. If the first master (master 0) asserts a request, it is awarded grant. Master 1 is given grant only if it requests the bus and master 0 doesn’t request the bus.

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VHDL Arbiter

arbiterWhat is an arbiter?

An arbiter is a very common block used on HW designs.

I think I can find the best example of an arbiter at home. I have only one car, and two young kids, both of them with their own driving licenses. On Friday and Saturday evenings, there will be usually a conflict over who gets to use the car. Usually it falls on me to arbiter who gets the car. Not an easy task.

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Altera FPGA at the wheel of an Audi A8

Audi announced its piloted driving technology at CES 2015. The Audi Prologue includes the Advanced Driver Assistance System Platform (zFAS), co-developed with TTTech.

The zFAS board is based on four devices: an Nvidia k1 processor and Infineon Aurix processor, Mobileye’s EyeQ3 for vision processing, and an Altera Cyclone V FPGA which provides sensor fusion, combining data from multiple sensors in the vehicle for highly reliable object detection and Deterministic Ethernet communications used to transport high bandwidth data within the vehicle.

The zFAS board receives and processes data from:

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Signed, unsigned and std_logic_vector

VHDL is a strong typed language. It is also a language which has quite a long history. These two facts together make handling of signed and unsigned numbers quite confusing. Even today I see lots of code examples with incorrect treatment of signed and unsigned arithmetic.

Part of the history of the VHDL language is the std_logic_arith library. This library is a non-standard library, or maybe I should say de-facto standard library, created by Sinopsis. I recommend not to use it, since there is an ieee library for arithmetic operations today, ieee.numeric
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Code Snippets reloaded

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The code snippets list is updated. Each example includes source code and testbench (downloadable). Now there are also proposals of exercises for you to solve. So if you were thinking what projects to make to enhance your VHDL knowledge, these exercises could be a nice option to try.

The list now includes:

Generic register with load

Generic down-counter

Generic up-down counter (includes exercises)

Binary to seven-segment decoder

Generic Demultiplexer / Decoder

Parallel to serial converter

Serial to parallel converter (includes exercises)

 

High Speed Serial I/O – free book

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This book was published by Xilinx in 2005. While in our very dynamic profession, some of the technologies explained can be a bit outdated, the basic concepts are there for anyone who wishes to learn or refresh his/her concepts about high speed serial links.

Inside the book you will find data about:

  • Serdes transceivers basics
  • 8b/10b, 64b/64b encoding
  • Clock recovery
  • Line equalization
  • Channel Bonding
  • Signal Integrity
  • Power considerations
  • Board design considerations, etc.

Book Title: High Speed Serial I/O made simple

Intel announces Xeon processor with FPGA accelerator

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Image source: Altera

Last year (December 2015), Intel completed the acquisition of Altera. As a result of this acquisition, the integration of processor and FPGA on a single chip is finally becoming a reality.

Intel envisions many applications for this combination of processor and FPGA. The FPGA will fulfill accelerator tasks, either by static configuration or dynamic reconfiguration.

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