VHDL or Verilog?

This question gets asked again and again, by beginners and experienced designers alike.

When I saw it posted on the FPGA group at reddit, I liked the answer from user fft32, so with his permission, I reproduce it here with some minor changes and additions.

vhdl_vs_verilog

 

VHDL compared to Verilog

VHDL:

  • A bit verbose, clunky syntax. I never liked that different constructs have different rules for the “end” tag, like “end synth” for architectures, versus “end component mux” for components. I always find myself looking up the syntax of packages and functions.
  • Strongly typed: It’s a bit of a pain to have to make a (0 downto 0) vector to do something like a carry-in, but at the end of the day, it can save you time debugging problems. You don’t scratch your head as to why your 10-bit vector is only 0 to 1, because you assigned a 1-bit value to it (a thing you could do in Verilog, but in VHDL would produce a compile error). Also, by default Verilog undeclared signals default to 1-bit nets. Once I acciddentaly did this with a clock and I was wondering why nothing worked.
  • Libraries: This is good and bad for me. It’s great to wrap your code in an organized and reusable manner. However, many “everyday” functions come from libraries rather than built into the language. There are non-standard libraries like std_logic_unsigned/std_logic_signed that are used in a lot of legacy code and old code examples. They’ve since been replaced by numeric_std. The conversion between types needs functions whose format is quite annoying.

Verilog:

  • Writing code seems more streamlined. No component declarations, loose data types (everything is just bits, really).
  • C-like syntax.
  • Resulting code is more compact.
  • Low-level descriptions are closer to actual hardware.
  • Verilog has a poor design of its concurrency resolution scheme. Being an HDL, concurrency is obviously a very important aspect. Here is a write up concerning this point.

 

At the end of the day, the two languages are really able to achieve the same designs. I think it’s good to understand code in both languages, but since mixed language support is common, I don’t see an issue sticking with the one that you prefer.

To the comments from fft32, I would add that in my opinion, Verilog with its plain syntax is easier to learn and grasp for the beginner.

Also, from my experience, Verilog tends to be dominant in the ASIC arena, while VHDL is the language of choice for most FPGA designs.

?And the winner is

Well, none of the two, at least as these words are written. In the long run, as you advance in your HDL designer career, you will be probably using both, although also probably using one of them most of the time.

If you are wondering which one you should start with, take the one that you feel more comfortable with. Or, ask colleagues and teachers which one is most needed in the market niche you want to be part of. The important thing is to grasp the structures behind the language, and not the language itself.

To be honest, it seems that both fft32 and me mostly used VHDL, so this comparison could be a little biased. But, after all, both languages are Hardware Description Languages. So what really matters are the flip-flops and gates that give life to your design, and not so much how in what language you describe them.

Whatever you choose, good luck!

 

One thought on “VHDL or Verilog?

  1. While you have to start somewhere, dont choose one and ignore the other. Plan to learn your way in both. My first taste was VHDL during college. I really did not like it then, and i dont think it was yet synthesizable for actual design to chip use. I next saw some Verilog and liked it better, but it was integration and verification, not rtl. Then back to VHDL again for a couple grad school courses. I probably know VHDL better now, but do want to go back to Verilog again.

    Also, even for VHDL users, you are likely to find a post-synthesis netlist is in Verilog format. So at least be ready to learn that much.

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