VHDL Arbiter

arbiterWhat is an arbiter?

An arbiter is a very common block used on HW designs.

I think I can find the best example of an arbiter at home. I have only one car, and two young kids, both of them with their own driving licenses. On Friday and Saturday evenings, there will be usually a conflict over who gets to use the car. Usually it falls on me to arbiter who gets the car. Not an easy task.

HW boards are not that different. There are at least two cases where a common (and valued, and expensive) resource is ‘wanted’ by several users:

  • Common memory: It is very usual to see boards where fast memory (i.e. DDR) is shared between a processor and an FPGA. Obviously a memory cannot answer to two masters at once. The processor, and the FPGA, ask the arbiter for permission to access the memory. Even if it is done at very high speed and simultaneously for our perception, in reality the FPGA and the processor have to take turns to own the memory. NOTE: There are other applications where even more than two ‘intelligent’ devices (processors, DSPs, FPGAs, ASICs) take turn accessing a common memory.
  • Common bus: Many times multiple masters (and slaves) communicate through a common bus. Electrically speaking the bus is very simple. It is no more than a set of copper connections, or wires (sometimes with bus drivers). But bus ownership is important, since it is impossible for two masters to own the bus at the same time (examples of multi-master buses: I2C, PCI). It two masters tried to ‘talk’ at the same time there would be a collision, and the data on the bus would be corrupted.

The arbiter is the piece of HW who decides who gets to use the common, valued resource, at any given time. However, and unlike the soccer arbiter, the VHDL arbiter will never take one of the devices out of the ‘game’ (well… almost never. There are cases where HW arbiters decide that one device is behaving badly and decide to get it out of the game. One example is a pluggable card accessing a common bus, that can be unplugged in a critical moment, and if the arbiter didn’t recognize the failure, the bus could remain stuck over the -now missing- device).

The arbiter receives two type of signals from its clients:

  • Request: Asserted by each one of the devices that want to own the common resource. There can be many request signals asserted at the same time, as is the case when many devices ask for permission to own the common resource.
  • Grant: Asserted by the arbiter, there is one grant signal for each master. Usually, there will be ONLY ONE grant signal asserted at any given time.

In the next installments we will see two examples of arbiters implemented in VHDL.

Read the second part of this article

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