SoC FPGA for IoT Edge Computing

Edge architecture from Fujisoft presented at ISDF 2016

One of the reasons for the explosive growth of IoT is that embedded devices with networking capabilities and sensor interfaces are cheap enough to deploy them at a plethora of locations.

However, network bandwidth is limited. Not only that, but also, the latency of the network can be of seconds or minutes. By the time the sensor data is acquired by the centralized computers, its value for decision making could be lost. In other words, for the IoT solution to be effective, it should not only deliver meaningful data securely (and filter it as much as possible to avoid network congestion), it should also analyze it and act upon it at the origination point of the data. At the very edge of the network.

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Timers Block – Part Three

On the previous entries of this series we already commented about:

In this third part of the series (as promised), we will show how to implement the timers block by using, not registers, but memory blocks.

Memory blocks are an often unused capability of modern FPGAs and can in many cases (as in this one) be a nice alternative to save on scarce resources like registers and LUTs. As we commented in the previous entry, implementing a block of 32 x 16 bit timers took about 7% of the LUTs of a Cyclone, and we wanted to see if we can reduce the quantity of resources taken.

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