Timers Block – Part Three

On the previous entries of this series we already commented about:

In this third part of the series (as promised), we will show how to implement the timers block by using, not registers, but memory blocks.

Memory blocks are an often unused capability of modern FPGAs and can in many cases (as in this one) be a nice alternative to save on scarce resources like registers and LUTs. As we commented in the previous entry, implementing a block of 32 x 16 bit timers took about 7% of the LUTs of a Cyclone, and we wanted to see if we can reduce the quantity of resources taken.

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