The VHDL code snippets list has two new additions:
Saturation counter, and
For each counter, source codes with explanations are provided, as well as test-bench, Modelsim project, waveform .do file, screenshots, etc.
All the files are released under GitHub.
Click here the complete list of VHDL code snippets.
Two new examples were added to the Code Snippets page:
Push button Debouncer
Parameterized PWM controller (includes exercises)
For the complete list of VHDL code examples, complete with sources and simulation files, check here. Some of the examples even include proposed exercises for you to try!
(FPGASite is featured @teamnotey – Follow me here )
This is certainly an incredible… what shall I call it? Machine? Demo? Learning tool?
Well… it was called the Megaprocessor by his creator, Mr. James Newman. See an intro to this very nice machine here:
Continue reading “Megaprocessor”
Are you going to make an FPGA design? Are you asking yourself where to start, how to continue, and finish?
These are the basic steps of an FPGA design flow:
Continue reading “FPGA Design Flow Summary”
An Entity defines the interface of a design unit. The elements of an entity are:
- Name of the entity
- Generic parameters
- Ports (connections of the entity)
- Most popular ports are of type in, out, and inout.
Continue reading “Component vs. Entity”
VHDL is a strong typed language. It is also a language which has quite a long history. These two facts together make handling of signed and unsigned numbers quite confusing. Even today I see lots of code examples with incorrect treatment of signed and unsigned arithmetic.
Part of the history of the VHDL language is the std_logic_arith library. This library is a non-standard library, or maybe I should say de-facto standard library, created by Sinopsis. I recommend not to use it, since there is an ieee library for arithmetic operations today, ieee.numeric
Continue reading “Signed, unsigned and std_logic_vector”
The code snippets list is updated. Each example includes source code and testbench (downloadable). Now there are also proposals of exercises for you to solve. So if you were thinking what projects to make to enhance your VHDL knowledge, these exercises could be a nice option to try.
The list now includes:
Generic register with load
Generic up-down counter (includes exercises)
Binary to seven-segment decoder
Generic Demultiplexer / Decoder
Parallel to serial converter
Serial to parallel converter (includes exercises)
Men marry women wishing they will never change, but they do.
Women marry men wishing they will be able to change them, but they don’t.
When I was young, even during my University studies, I was a real disaster in anything related to order. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to say: – “In the disorder, I know where everything is. When my mother makes some order, I can’t find anything”.
And to demonstrate that the half-joke at the beginning of this article is not true, I must say that I changed a lot since I married. My home won’t appear in a decoration magazine, but it is not close at all to my young-days’ complete-mess room.
Continue reading “Keeping your design files organized”
This question gets asked again and again, by beginners and experienced designers alike.
When I saw it posted on the FPGA group at reddit, I liked the answer from user fft32, so with his permission, I reproduce it here with some minor changes and additions.
VHDL compared to Verilog
Continue reading “VHDL or Verilog?”
There are several code snippets available here.
Go check them out!