Signed, unsigned and std_logic_vector

VHDL is a strong typed language. It is also a language which has quite a long history. These two facts together make handling of signed and unsigned numbers quite confusing. Even today I see lots of code examples with incorrect treatment of signed and unsigned arithmetic.

Part of the history of the VHDL language is the std_logic_arith library. This library is a non-standard library, or maybe I should say de-facto standard library, created by Sinopsis. I recommend not to use it, since there is an ieee library for arithmetic operations today, ieee.numeric
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Code Snippets reloaded

code1

The code snippets list is updated. Each example includes source code and testbench (downloadable). Now there are also proposals of exercises for you to solve. So if you were thinking what projects to make to enhance your VHDL knowledge, these exercises could be a nice option to try.

The list now includes:

Generic register with load

Generic down-counter

Generic up-down counter (includes exercises)

Binary to seven-segment decoder

Generic Demultiplexer / Decoder

Parallel to serial converter

Serial to parallel converter (includes exercises)

 

Keeping your design files organized

Men marry women wishing they will never change, but they do.
Women marry men wishing they will be able to change them, but they don’t.

When I was young, even during my University studies, I was a real disaster in anything related to order. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to say: – “In the disorder, I know where everything is. When my mother makes some order, I can’t find anything”.

And to demonstrate that the half-joke at the beginning of this article is not true, I must say that I changed a lot since I married. My home won’t appear in a decoration magazine, but it is not close at all to my young-days’ complete-mess room.

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