In this third part of the series (as promised), we will show how to implement the timers block by using, not registers, but memory blocks.
Memory blocks are an often unused capability of modern FPGAs and can in many cases (as in this one) be a nice alternative to save on scarce resources like registers and LUTs. As we commented in the previous entry, implementing a block of 32 x 16 bit timers took about 7% of the LUTs of a Cyclone, and we wanted to see if we can reduce the quantity of resources taken.
On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files.
Chapter 5 – Matlab Formal Verification
Our VHDL block implements an algorithm that generates pseudo-random numbers. If the register is large enough, the output of the block will be hundreds or thousands of different numbers. How can we be sure that our block is working OK?
On the first part of this tutorial, we started with a simple implementation of an LFSR block (Chapter 1) and it test bench (Chapter 2). Let’s make our code a bit more professional.
Chapter 3 – Upgrading the LFSR code
Good code doesn’t use hard-coded constants as were used on the first part (to define the LFSR width). The downside of using constants is that code updates and maintenance is cumbersome at best. If we want to change the width of the register… we must scan the code and change each and every instance of the constant. There is a great possibility of making mistakes while doing that. Forgetting to change one of the ‘3’s… or changing one that was not related to the register width. This is not clearly seen in a short piece of code, but as our code gets longer, maintaining hard-coded constants is a sure recipe for trouble.
In this tutorial we will see how to design a block. We will start with a very simple block and gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see:
How to start with a simple block and gradually add features and improvements
How to add a test bench (simulation)
Adding parameters to the VHDL block
Saving the block data output to files (from simulation)
The first in the projects for the BeMicro CV board will be a HW LED flasher. Although the design is very easy, it is a complete design including absolutely all the elements needed to achieve a reliable design with timing closure.
For an introduction about the Be Micro CV evaluation board, please refer to this post.
What will the project do:
Flash a sequence of LEDs by dividing the clock input
Make a ‘lamp test’ (all LEDs lit) when reset is pressed
LEDs sequence is accelerated if the user presses the second push button on the board.
This is the third part of a series of articles on VHDL arbiters.
On the first part, we commented what a VHDL arbiter is.
On the second part, we saw the VHDL code for a fixed priority VHDL arbiter.
When I talked about what a VHDL arbiter is, I gave the example of the single car we have at home, and how I have to decide who gets to use the car on next Friday evening. In a typical situation, if both children ask for the car, the first thing they will account for is, who got the car the last time.