Pseudo random generator Tutorial – Part 3

On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files.

Chapter 5 – Matlab Formal Verification

Our VHDL block implements an algorithm that generates pseudo-random numbers. If the register is large enough, the output of the block will be hundreds or thousands of different numbers. How can we be sure that our block is working OK?

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TI power solution for Arria 10 GX


“Field programmable gate arrays (FPGAs) are increasingly complex system on chips (SoCs) that include not just programmable logic gates and random access memory (RAM) but also analog-to-digital converters (ADCs); digital-to-analog converters (DACs); and programmable analog features and signal-conditioning circuits that enable high-performance digital computations in servers, network-attached storage (NAS), enterprise switches, oscilloscopes, network analyzers, test equipment and software-defined radios.”

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Pseudo random generator Tutorial – Part 2


Modelsim Altera running an LFSR simulation

On the first part of this tutorial, we started with a simple implementation of an LFSR block (Chapter 1) and it test bench (Chapter 2). Let’s make our code a bit more professional.

Chapter 3 – Upgrading the LFSR code

Good code doesn’t use hard-coded constants as were used on the first part (to define the LFSR width). The downside of using constants is that code updates and maintenance is cumbersome at best. If we want to change the width of the register… we must scan the code and change each and every instance of the constant. There is a great possibility of making mistakes while doing that. Forgetting to change one of the ‘3’s… or changing one that was not related to the register width. This is not clearly seen in a short piece of code, but as our code gets longer, maintaining hard-coded constants is a sure recipe for trouble.

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Pseudo random generator Tutorial

Modelsim Altera running an LFSR simulation

In this tutorial we will see how to design a block. We will start with a very simple block and gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see:

  • How to start with a simple block and gradually add features and improvements
  • How to add a test bench (simulation)
  • Adding parameters to the VHDL block
  • Saving the block data output to files (from simulation)
  • Importing the files to Matlab in order to:
    • Verify the results (Formal testing), and
    • Analyze the results (in this case, using FFT)

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MIF_Gen – A Matlab Utility


Many times I find myself in the need of generating data for testing. We need data for verification, either done on simulation or on the real target.

One easy way to test our system is to generate data vectors on RAM. Altera RAM IP includes the ability to initialize RAM contents during power-up by means of a .hex file.

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