FPGA Site projects on GitHub

From now on, projects released on FPGA SIte will be available on GitHub. In this way, I hope that the projects will be better mantained (with versioning) and in a standardized format.

For any project, the following directories will be included under GitHub:

  • src – VHDL source files
    • ip – Special VHDL files generated by Intel/Altera IP Wizard
  • sim – Simulation files for Modelsim Altera (including  .mpf project file and wave.do – waveform generating do file)
    • wfm – Screenshots of waveforms from simulation runs
  • tb – VHDL (and other) files for test-benching

The tree for the projects can be seen here

 

SoC FPGA for IoT Edge Computing

edge_iot
Edge architecture from Fujisoft presented at ISDF 2016

One of the reasons for the explosive growth of IoT is that embedded devices with networking capabilities and sensor interfaces are cheap enough to deploy them at a plethora of locations.

However, network bandwidth is limited. Not only that, but also, the latency of the network can be of seconds or minutes. By the time the sensor data is acquired by the centralized computers, its value for decision making could be lost. In other words, for the IoT solution to be effective, it should not only deliver meaningful data securely (and filter it as much as possible to avoid network congestion), it should also analyze it and act upon it at the origination point of the data. At the very edge of the network.

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Timers Block – Part Three

On the previous entries of this series we already commented about:

In this third part of the series (as promised), we will show how to implement the timers block by using, not registers, but memory blocks.

Memory blocks are an often unused capability of modern FPGAs and can in many cases (as in this one) be a nice alternative to save on scarce resources like registers and LUTs. As we commented in the previous entry, implementing a block of 32 x 16 bit timers took about 7% of the LUTs of a Cyclone, and we wanted to see if we can reduce the quantity of resources taken.

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FPGAs and Deep Machine Learning

machine-learning

The concept of machine learning is not new. Attempts at systems emulating intelligent behavior, like expert systems, go as far back as the early 1980’s. And the very notion of modern Artificial Intelligence has a long history. The name itself was coined at a Dartmouth College conference (1956), but the idea of an “electronic brain” was born together with the development of modern computers. AI as an idea accompanies us from the dawn of human history.

Three latest development are pushing forward “Machine Learning”:

  • Powerful distributed processors
  • Cheap and high volume storage
  • High bandwidth interconnection to bring the data to the processors

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TI power solution for Arria 10 GX

ti_arria_power

“Field programmable gate arrays (FPGAs) are increasingly complex system on chips (SoCs) that include not just programmable logic gates and random access memory (RAM) but also analog-to-digital converters (ADCs); digital-to-analog converters (DACs); and programmable analog features and signal-conditioning circuits that enable high-performance digital computations in servers, network-attached storage (NAS), enterprise switches, oscilloscopes, network analyzers, test equipment and software-defined radios.”

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MIF_Gen – A Matlab Utility

matlab_mif_gen

Many times I find myself in the need of generating data for testing. We need data for verification, either done on simulation or on the real target.

One easy way to test our system is to generate data vectors on RAM. Altera RAM IP includes the ability to initialize RAM contents during power-up by means of a .hex file.

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Linear Power Solutions for FPGAs

Aria10_GX_FPGA_Development_Kit_1
Altera Arria 10 Evaluation board – Source: Linear

Modern FPGA devices are quite complex machines. They include support for several type of I/Os at different voltages (LVCMOS, LVDS, SSTL, etc). Also, the FPGA core usually works at low voltages of around 1.0V, but at quite high currents of several amperes. Additionally, power sequencing requirements must be met.

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BeMicro CV – HW & SW LED flasher

The second project for the BeMicro CV board will be a HW/SW LED flasher. From the LEDs present in the board, some will be flashed by HW, and others will be flashed by SW running on a NIOS processor.

For an introduction about the Be Micro CV evaluation board, please refer to this post.

What will the project do:

  1. Flash a sequence of HW LEDs by dividing the clock input
  2. Make a ‘lamp test’ (all LEDs lit) when reset is pressed
  3. LEDs sequence is accelerated if the user presses the second push button on the board.
  4. Three LEDs are flashed by SW. To differentiate between the two groups, the LEDs flashed by SW run faster.

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