VHDL Arbiter – part II

In the previous installment, we defined what a HW arbiter is. Let’s see a simple implementation of a VHDL arbiter.

The arbiter has three inputs and three outputs.

The logic is very simple. If the first master (master 0) asserts a request, it is awarded grant. Master 1 is given grant only if it requests the bus and master 0 doesn’t request the bus.

Continue reading “VHDL Arbiter – part II”

Code Snippets reloaded

code1

The code snippets list is updated. Each example includes source code and testbench (downloadable). Now there are also proposals of exercises for you to solve. So if you were thinking what projects to make to enhance your VHDL knowledge, these exercises could be a nice option to try.

The list now includes:

Generic register with load

Generic down-counter

Generic up-down counter (includes exercises)

Binary to seven-segment decoder

Generic Demultiplexer / Decoder

Parallel to serial converter

Serial to parallel converter (includes exercises)