Xilinx announces new RFSoC devices

On February 21st Xilinx announced new devices aimed for the design of solutions for 5G wireless systems. The announced RFSoC devices will combine existing MPSoC capabilities with integrated ADCs and DACs.

The integrated 16nm-based RF data conversion technology includes:

  • Direct RF sampling
  • 12-bit ADCs at up to 4GSPS, with digital down-conversion
  • 14-bit DACs at up to 6.4GSPS, with digital up-conversion

Current solutions for SDR are typically based on superhet transceivers. This architecture needs:

  • IF stage including LO
  • High speed converters, typically needing fast SerDes (JESD204) to interconnect the processing FPGA to the ADC and DAC

Direct RF Sampling Receiver – Source: Xilinx

Xilinx proposed architecture with integrated DAC and ADC as well as direct RF sampling simplifies and enhances the SDR solution implementation:

  • Reduced noise
  • Reduced power consumption
  • Reduced PCB size and routing complexity

As of the date of this article, there is no public information regarding availability dates and/or device types for the new RFSoCs.

FPGA Site projects on GitHub

From now on, projects released on FPGA SIte will be available on GitHub. In this way, I hope that the projects will be better mantained (with versioning) and in a standardized format.

For any project, the following directories will be included under GitHub:

  • src – VHDL source files
    • ip – Special VHDL files generated by Intel/Altera IP Wizard
  • sim – Simulation files for Modelsim Altera (including  .mpf project file and wave.do – waveform generating do file)
    • wfm – Screenshots of waveforms from simulation runs
  • tb – VHDL (and other) files for test-benching

The tree for the projects can be seen here


SoC FPGA for IoT Edge Computing

Edge architecture from Fujisoft presented at ISDF 2016

One of the reasons for the explosive growth of IoT is that embedded devices with networking capabilities and sensor interfaces are cheap enough to deploy them at a plethora of locations.

However, network bandwidth is limited. Not only that, but also, the latency of the network can be of seconds or minutes. By the time the sensor data is acquired by the centralized computers, its value for decision making could be lost. In other words, for the IoT solution to be effective, it should not only deliver meaningful data securely (and filter it as much as possible to avoid network congestion), it should also analyze it and act upon it at the origination point of the data. At the very edge of the network.

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Timers Block – Part Three

On the previous entries of this series we already commented about:

In this third part of the series (as promised), we will show how to implement the timers block by using, not registers, but memory blocks.

Memory blocks are an often unused capability of modern FPGAs and can in many cases (as in this one) be a nice alternative to save on scarce resources like registers and LUTs. As we commented in the previous entry, implementing a block of 32 x 16 bit timers took about 7% of the LUTs of a Cyclone, and we wanted to see if we can reduce the quantity of resources taken.

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FPGAs and Deep Machine Learning


The concept of machine learning is not new. Attempts at systems emulating intelligent behavior, like expert systems, go as far back as the early 1980’s. And the very notion of modern Artificial Intelligence has a long history. The name itself was coined at a Dartmouth College conference (1956), but the idea of an “electronic brain” was born together with the development of modern computers. AI as an idea accompanies us from the dawn of human history.

Three latest development are pushing forward “Machine Learning”:

  • Powerful distributed processors
  • Cheap and high volume storage
  • High bandwidth interconnection to bring the data to the processors

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Pseudo random generator Tutorial – Part 3

On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files.

Chapter 5 – Matlab Formal Verification

Our VHDL block implements an algorithm that generates pseudo-random numbers. If the register is large enough, the output of the block will be hundreds or thousands of different numbers. How can we be sure that our block is working OK?

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TI power solution for Arria 10 GX


“Field programmable gate arrays (FPGAs) are increasingly complex system on chips (SoCs) that include not just programmable logic gates and random access memory (RAM) but also analog-to-digital converters (ADCs); digital-to-analog converters (DACs); and programmable analog features and signal-conditioning circuits that enable high-performance digital computations in servers, network-attached storage (NAS), enterprise switches, oscilloscopes, network analyzers, test equipment and software-defined radios.”

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