On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files.
Chapter 5 – Matlab Formal Verification
Our VHDL block implements an algorithm that generates pseudo-random numbers. If the register is large enough, the output of the block will be hundreds or thousands of different numbers. How can we be sure that our block is working OK?
On the first part of this tutorial, we started with a simple implementation of an LFSR block (Chapter 1) and it test bench (Chapter 2). Let’s make our code a bit more professional.
Chapter 3 – Upgrading the LFSR code
Good code doesn’t use hard-coded constants as were used on the first part (to define the LFSR width). The downside of using constants is that code updates and maintenance is cumbersome at best. If we want to change the width of the register… we must scan the code and change each and every instance of the constant. There is a great possibility of making mistakes while doing that. Forgetting to change one of the ‘3’s… or changing one that was not related to the register width. This is not clearly seen in a short piece of code, but as our code gets longer, maintaining hard-coded constants is a sure recipe for trouble.
In this tutorial we will see how to design a block. We will start with a very simple block and gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see:
How to start with a simple block and gradually add features and improvements
How to add a test bench (simulation)
Adding parameters to the VHDL block
Saving the block data output to files (from simulation)
A good VHDL editor is terribly important during all the phases of your design cycle.
Both Altera Quartus and Modelsim simulator include their own VHDL editors. Both tools include syntax highlighting. In the case of Altera Quartus editor, there is a very useful feature which is the possibility of entering templates for commonly used code blocks (entity, architecture, component) and also for design units (counters, registers, memories, etc.).
This is the third part of a series of articles on VHDL arbiters.
On the first part, we commented what a VHDL arbiter is.
On the second part, we saw the VHDL code for a fixed priority VHDL arbiter.
When I talked about what a VHDL arbiter is, I gave the example of the single car we have at home, and how I have to decide who gets to use the car on next Friday evening. In a typical situation, if both children ask for the car, the first thing they will account for is, who got the car the last time.
Men marry women wishing they will never change, but they do. Women marry men wishing they will be able to change them, but they don’t.
When I was young, even during my University studies, I was a real disaster in anything related to order. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to say: – “In the disorder, I know where everything is. When my mother makes some order, I can’t find anything”.
And to demonstrate that the half-joke at the beginning of this article is not true, I must say that I changed a lot since I married. My home won’t appear in a decoration magazine, but it is not close at all to my young-days’ complete-mess room.