Timers Block – Part Three

On the previous entries of this series we already commented about:

In this third part of the series (as promised), we will show how to implement the timers block by using, not registers, but memory blocks.

Memory blocks are an often unused capability of modern FPGAs and can in many cases (as in this one) be a nice alternative to save on scarce resources like registers and LUTs. As we commented in the previous entry, implementing a block of 32 x 16 bit timers took about 7% of the LUTs of a Cyclone, and we wanted to see if we can reduce the quantity of resources taken.

Continue reading “Timers Block – Part Three”

BeMicro CV – HW & SW LED flasher

The second project for the BeMicro CV board will be a HW/SW LED flasher. From the LEDs present in the board, some will be flashed by HW, and others will be flashed by SW running on a NIOS processor.

For an introduction about the Be Micro CV evaluation board, please refer to this post.

What will the project do:

  1. Flash a sequence of HW LEDs by dividing the clock input
  2. Make a ‘lamp test’ (all LEDs lit) when reset is pressed
  3. LEDs sequence is accelerated if the user presses the second push button on the board.
  4. Three LEDs are flashed by SW. To differentiate between the two groups, the LEDs flashed by SW run faster.

Continue reading “BeMicro CV – HW & SW LED flasher”

BeMicro CV – HW LED flasher

The first in the projects for the BeMicro CV board will be a HW LED flasher. Although the design is very easy, it is a complete design including absolutely all the elements needed to achieve a reliable design with timing closure.

For an introduction about the Be Micro CV evaluation board, please refer to this post.

What will the project do:

  1. Flash a sequence of LEDs by dividing the clock input
  2. Make a ‘lamp test’ (all LEDs lit) when reset is pressed
  3. LEDs sequence is accelerated if the user presses the second push button on the board.

Continue reading “BeMicro CV – HW LED flasher”

VHDL editors – Notepad++

A good VHDL editor is terribly important during all the phases of your design cycle.

Both Altera Quartus and Modelsim simulator include their own VHDL editors. Both tools include syntax highlighting. In the case of Altera Quartus editor, there is a very useful feature which is the possibility of entering templates for commonly used code blocks (entity, architecture, component) and also for design units (counters, registers, memories, etc.).

Continue reading “VHDL editors – Notepad++”

VHDL Arbiter – part II

In the previous installment, we defined what a HW arbiter is. Let’s see a simple implementation of a VHDL arbiter.

The arbiter has three inputs and three outputs.

The logic is very simple. If the first master (master 0) asserts a request, it is awarded grant. Master 1 is given grant only if it requests the bus and master 0 doesn’t request the bus.

Continue reading “VHDL Arbiter – part II”

Keeping your design files organized

Men marry women wishing they will never change, but they do.
Women marry men wishing they will be able to change them, but they don’t.

When I was young, even during my University studies, I was a real disaster in anything related to order. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to say: – “In the disorder, I know where everything is. When my mother makes some order, I can’t find anything”.

And to demonstrate that the half-joke at the beginning of this article is not true, I must say that I changed a lot since I married. My home won’t appear in a decoration magazine, but it is not close at all to my young-days’ complete-mess room.

Continue reading “Keeping your design files organized”