VHDL Arbiter – part II

In the previous installment, we defined what a HW arbiter is. Let’s see a simple implementation of a VHDL arbiter.

The arbiter has three inputs and three outputs.

The logic is very simple. If the first master (master 0) asserts a request, it is awarded grant. Master 1 is given grant only if it requests the bus and master 0 doesn’t request the bus.

Continue reading “VHDL Arbiter – part II”