Signed, unsigned and std_logic_vector

VHDL is a strong typed language. It is also a language which has quite a long history. These two facts together make handling of signed and unsigned numbers quite confusing. Even today I see lots of code examples with incorrect treatment of signed and unsigned arithmetic.

Part of the history of the VHDL language is the std_logic_arith library. This library is a non-standard library, or maybe I should say de-facto standard library, created by Sinopsis. I recommend not to use it, since there is an ieee library for arithmetic operations today, ieee.numeric
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