In this third part of the series (as promised), we will show how to implement the timers block by using, not registers, but memory blocks.
Memory blocks are an often unused capability of modern FPGAs and can in many cases (as in this one) be a nice alternative to save on scarce resources like registers and LUTs. As we commented in the previous entry, implementing a block of 32 x 16 bit timers took about 7% of the LUTs of a Cyclone, and we wanted to see if we can reduce the quantity of resources taken.
Author Mike Fields wrote this book as an introduction to FPGAs and VHDL. The book examples are mainly oriented to Xilinx Spartan 3E FPGA (but as in other books, the concepts are general. If you don’t have that FPGA, adapting the book examples to your own device can be an excellent way to learn).
The first in the projects for the BeMicro CV board will be a HW LED flasher. Although the design is very easy, it is a complete design including absolutely all the elements needed to achieve a reliable design with timing closure.
For an introduction about the Be Micro CV evaluation board, please refer to this post.
What will the project do:
Flash a sequence of LEDs by dividing the clock input
Make a ‘lamp test’ (all LEDs lit) when reset is pressed
LEDs sequence is accelerated if the user presses the second push button on the board.